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DATA SHEET
PD77113A, 77114
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs). Compared with the PD77016 family, these DSPs have improved power consumption and are ideal for batterypowered mobile terminals such as PDAs and cellular phones. Both mask ROM and RAM models are available. For details of the functions of these DSPs, refer to the following User's Manuals:
PD77111 Family User's Manual
: U14623E
PD77016 Family User's Manual - Instructions : U13116E
FEATURES
z Instruction cycle (operating clock)
PD77113A : 13.3 ns MIN (75 MHz MAX) PD77114 : 13.3 ns MIN (75 MHz MAX)
z Memory * Internal instruction memory
PD77113A : RAM 3.5K words x 32 bits
Mask ROM 48K words x 32 bits
PD77114 : RAM 3.5K words x 32 bits
Mask ROM 48K words x 32 bits * Data memory
PD77113A : RAM 16K words x 16 bits x 2 banks
Mask ROM 32K words x 16 bits x 2 banks
PD77114 : RAM 16K words x 16 bits x 2 banks
Mask ROM 32K words x 16 bits x 2 banks External memory space 8K words x 16 bits x 2 banks
ORDERING INFORMATION
Part Number Package 80-pin plastic fine-pitch BGA (9 x 9) 100-pin plastic TQFP (fine pitch) (14 x 14)
PD77113AF1-xxx-CN1 PD77114GC-xxx-9EU
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14373EJ3V0DS00 (3rd edition) Date Published February 2001 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1999
2
X bus Y bus X memory Y memory data addressing unit Y memory R0 - R7 Data memory unit Main bus MAC 16 x 16 + 40 40 ALU (40) BSFT Program control unit Loop control stack PC stack Instruction memory Operation unit CPU control PLL RESET CLKOUT WAKEUPNote CLKIN
BLOCK DIAGRAM
External memory
Peripheral units
Serial I/O #1
X memory data addressing unit
Serial I/O #2
Data Sheet U14373EJ3V0DS
Port
Host I/O
Interrupt control
Wait controller
INT1 - INT4Note
Note option.
PD77113A, 77114
IE I/O
The WAKEUP pin is multiplexed with the INT4 pin. The function of the WAKEUP pin can be activated or deactivated by mask
PD77113A, 77114
PIN CONFIGURATION
+2.5 V +3 V
Serial interface #1
SO1 SORQ1 SOEN1 SCK1 SI1 SIEN1 SIAK1 SO2 SOEN2 SCK2 SI2 SIEN2 (4) P0 - P3
IVDD
EVDD RESET INT1 - INT4 Reset, interrupt (4)
CLKIN CLKOUT
Clock
Serial interface #2
WAKEUPNote 1
System control
Port
(2) Host interface
(8) For debugging (2) (4)
HCS HA0, HA1 HRD HRE HWR HWE HD0 - HD7 TDO, TICE TCK, TDI, TMS, TRST GND
DA0 - DA12 X/Y D0 - D15 MRD MWR HOLDRQ HOLDAK BSTB
(13) External data (16) memory Note 2
Data bus control
Notes 1. The function of this pin can be activated or deactivated by mask option. 2. An external data memory interface is not provided on the PD77113A.
Data Sheet U14373EJ3V0DS
3
4
DSP FUNCTION LIST
Item Memory space Internal instruction RAM (words x bits) Internal instruction ROM Data RAM (X/Y memory) Data ROM (X/Y memory) External instruction memory
Data Sheet U14373EJ3V0DS
PD77016
1.5K x 32 None 2K x 16 each
PD77018A
256 x 32
PD77019
PD77019-013
PD77110
35.5K x 32
PD77111
PD77112
PD77113A
PD77114
4K x 32 24K x 32 3K x 16 each None
1K x 32 31.75K x 32 3K x 16 each
3.5K x 32 48K x 32 16K x 16 each
24K x 16 each
None
12K x 16 each
None
16K x 16 each
32K x 16 each
48K x 32
None
External data memory (X/Y memory) Instruction cycle (at maximum speed) Multiple
48K x 16 each
16K x 16 each
32K x 16 each
None
16K x 16 each
None
8K x 16 each
30 ns (33 MHz) -
16.6 ns (60 MHz) x1, 2, 3, 4, 8 (mask option) Fixed to x4
15.3 ns (65 MHz) Integer of x1 to 8 (external pin)
13.3 ns (75 MHz) Integer of x1 to 16 (mask option)
Serial interface (two channels)
Channels 1 and 2 Channel 1 has same function as PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec). have same function. 5V 3V DSP core: 2.5 V I/O pins : 3 V 100-pin TQFP 80-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin FBGA 100-pin TQFP
Supply voltage
Package
160-pin QFP
100-pin TQFP 116-pin BGA
PD77113A, 77114
PD77113A, 77114
PIN CONFIGURATION
80-pin plastic fine-pitch BGA (9 x 9)
PD77113AF1-xxx-CN1
(Bottom View) 9 8 7 6 5 4 3 2 1 J H G F E D C B A A B C D E F G H J (Top View)
Index mark
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 - NU
Pin Name
Pin No. C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5
Note
Pin Name NU RESET TDI TDO CLKIN HA0 EVDD EVDD NU INT2 NU TCK GND HWR HRD EVDD NU GND SIAK1 NU
Pin No. E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7
Pin Name HCS GND HD1 HD2 NU NU SOEN1 GND HD0 SI2 HD3 HD6 HD5 EVDD GND SIEN1 SO1 IVDD HD4 P2
Pin No. G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 P1
Pin Name
GND NU NU SCK1 SOEN2 SIEN2 P3 P0 HD7 NU - NU SI1 SORQ1 SO2 SCK2 EVDD NU -
EVDD INT3 GND TMS GND TRST - NU NU INT1 INT4/WAKEUP IVDD TICE IVDD HA1 CLKOUT GND NU
D6 D7 D8 D9 E1 E2 E3 E4
Note The function of the WAKEUP pin can be activated or deactivated by a mask option.
Data Sheet U14373EJ3V0DS
5
PD77113A, 77114
100-pin plastic TQFP (fine-pitch) (14 x 14) (Top View)
PD77114GC-xxx-9EU
EVDD X/Y I.C. MRD MWR NC BSTB HOLDAK HOLDRQ INT1 INT2 INT3 INT4/WAKEUPNote RESET GND IVDD TRST TMS TDI TCK TICE TDO GND IVDD GND
GND NC NC DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 D15 D14 D13 D12 D11 D10 D9 D8 EVDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EVDD CLKIN CLKOUT HA1 HA0 HWR HRD HCS HWE HRE GND EVDD HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 P0 P1 P2 P3 GND
Note The functions can be activated or deactivated by a mask option.
6
GND D7 D6 D5 D4 D3 D2 D1 D0 IVDD GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 SCK2 SIEN2 SI2 NC EVDD
Data Sheet U14373EJ3V0DS
PD77113A, 77114
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name GND NC NC DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 D15 D14 D13 D12 D11 D10 D9 D8 EVDD Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name GND D7 D6 D5 D4 D3 D2 D1 D0 IVDD GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 SCK2 SIEN2 SI2 NC EVDD Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name GND P3 P2 P1 P0 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 EVDD GND HRE HWE HCS HRD HWR HA0 HA1 CLKOUT CLKIN EVDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name GND IVDD GND TDO TICE TCK TD1 TMS TRST IVDD GND RESET INT4/WAKEUP INT3 INT2 INT1 HOLDRQ HOLDAK BSTB NC MWR MRD I.C. X/Y EVDD
Note
Note The function of the WAKEUP pin can be activated or deactivated by a mask option.
Data Sheet U14373EJ3V0DS
7
PD77113A, 77114
PIN NAME
BSTB CLKIN CLKOUT D0 - D15 DA0 - DA12 EVDD GND HA0, HA1 HCS HD0 - HD7 HOLDAK HOLDRQ HRD HRE HWE HWR I.C. INT1 - INT4 IVDD MRD MWR NC NU P0 - P3 RESET SCK1, SCK2 SI1, SI2 SIAK1 SIEN1, SIEN2 SO1, SO2 SORQ1 TCK TDI TDO TICE TMS TRST WAKEUP X/Y : Bus Strobe : Clock Input : Clock Output : 16-bit Data Bus : External Data Memory Address Bus : Power Supply for I/O Pins : Ground : Host Data Access : Host Chip Select : Host Data Bus : Hold Acknowledge : Hold Request : Host Read : Host Read Enable : Host Write Enable : Host Write : Internally Connected : Interrupt : Power Supply for DSP Core : Memory Read Output : Memory Write Output : Non-Connection : Not Used : Port : Reset : Serial Clock Input : Serial Data Input : Serial Input Acknowledge : Serial Input Enable : Serial Data Output : Serial Output Request : Test Clock Input : Test Data Input : Test Data Output : Test In-Circuit Emulator : Test Mode Select : Test Reset : Wakeup from STOP Mode : X/Y Memory Select
SOEN1, SOEN2 : Serial Output Enable
8
Data Sheet U14373EJ3V0DS
PD77113A, 77114
CONTENTS 1. PIN FUNCTION ................................................................................................................................. 1.1 Pin Function Description.......................................................................................................... 1.2 Connection of Unused Pins ..................................................................................................... 2. FUNCTION OUTLINE ....................................................................................................................... 2.1 Program Control Unit ................................................................................................................ 2.2 Arithmetic Unit........................................................................................................................... 2.3 Data Memory Unit ...................................................................................................................... 2.4 Peripheral Units ......................................................................................................................... 3. CLOCK GENERATOR ...................................................................................................................... 4. RESET FUNCTION ........................................................................................................................... 4.1 Hardware Reset ......................................................................................................................... 4.2 Initializing PLL ........................................................................................................................... 5. FUNCTIONS OF BOOT-UP ROM................................................................................................... 5.1 Boot at Reset ............................................................................................................................. 5.2 Reboot ........................................................................................................................................ 5.3 Signature Operation .................................................................................................................. 5.4 Instruction ROM Modification .................................................................................................. 6. STANDBY MODES ........................................................................................................................... 6.1 HALT Mode................................................................................................................................. 6.2 STOP Mode ................................................................................................................................ 7. MEMORY MAP.................................................................................................................................. 7.1 Instruction Memory ................................................................................................................... 7.2 Data Memory .............................................................................................................................. 8. MASK OPTION ................................................................................................................................. 8.1 Clock Control Options .............................................................................................................. 8.2 WAKEUP Function .................................................................................................................... 9. INSTRUCTIONS................................................................................................................................. 9.1 Outline of Instructions .............................................................................................................. 9.2 Instruction Set and Operation.................................................................................................. 10. ELECTRICAL SPECIFICATIONS..................................................................................................... 11. PACKAGE DRAWINGS.................................................................................................................... 12. RECOMMENDED SOLDERING CONDITIONS............................................................................... 10 10 15 17 17 18 19 19 20 20 20 21 21 21 22 23 23 24 24 24 25 25 27 28 28 29 30 30 31 37 56 58
Data Sheet U14373EJ3V0DS
9
PD77113A, 77114
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
* Power supply
Pin No. Pin Name 100-pin TQFP IVDD EVDD 35, 77, 85 25, 50, 64, 75, 100 1, 26, 36, 51, 65, 76, 78, 86 80-pin BGA B5, B7, G5 A3, C9, D1, D9, G1, J7 A5, A7, C1, D6, E2, E7, F4, G2, G9 - - - Power to DSP core (+2.5 V) Power to I/O pins (+3 V) - - - I/O Function Shared by:
GND
Ground
Remark Please supply voltage to the IVDD and EVDD pins simultaneously. * System control
Pin No. Pin Name 100-pin TQFP CLKIN CLKOUT RESET WAKEUP 74 73 87 88 80-pin BGA C7 B9 C4 B4 Input Output Input Input System clock input Internal system clock output Internal system reset signal input Stop mode release signal input. * When this pin is asserted active, the stop mode is released. The function of this pin can be activated or deactivated by a mask option. INT4 - - I/O Function Shared by:
* Interrupt
Pin No. Pin Name 100-pin TQFP INT1 - INT3 INT4 91 - 89 88 80-pin BGA B3, D3, A4 B4 Input Input External maskable interrupt input. * Detected at the falling edge. - WAKEUP I/O Function Shared by:
10
Data Sheet U14373EJ3V0DS
PD77113A, 77114
* External data memory interface (PD77114 only)
Pin No. Pin Name 100-pin TQFP X/Y 99 80-pin BGA - Output (3S) Memory select signal output. 0: Uses X memory. 1: Uses Y memory. Address bus of external data memory. * Accesses the external memory. * Continuously outputs the external memory address accessed last when the external memory is not being accessed. Kept low (0x000) if the external memory is never accessed after reset. 16-bit data bus. * Accesses the external memory. Read output * External memory read Write output * External memory write Hold request signal * Input a low level to this pin when the external device uses the external data memory bus of the PD77114. Bus strobe signal * This pin goes low when the PD77114 uses the external data memory bus. Hold acknowledge signal * This pin goes low when the external device is enabled to use the external data memory bus of the PD77114. - I/O Function Shared by:
DA0 - DA12
16 - 4
-
Output (3S)
-
D0 - D15
34 - 27, 24 - 17
- - - -
I/O (3S) Output (3S) Output (3S) Input
- - - -
MRD
97
MWR
96
HOLDRQ
92
BSTB
94
-
Output
-
HOLDAK
93
-
Output
-
Remark Pins marked "3S" under the heading "I/O" go into a high-impedance state in the following conditions: X/Y, DA0-DA12, MRD, MWR: When the bus is released (HOLDAK = low level) D0-D15: When the external data memory is not being accessed and when the bus is released (HOLDAK = low level)
Data Sheet U14373EJ3V0DS
11
PD77113A, 77114
* Serial interface
Pin No. Pin Name 100-pin TQFP SCK1 SORQ1 SOEN1 SO1 39 42 43 41 80-pin BGA H3 J4 F3 G4 Input Output Input Output (3S) Input Input Output Input Input Output (3S) Input Input Serial 1 clock input Serial output 1 request Serial output 1 enable Serial data output 1 - - - - - - - - - - - - I/O Function Shared by:
SIEN1 SI1 SIAK1 SCK2 SOEN2 SO2
38 37 40 46 44 45
G3 J3 E3 J6 H4 J5
Serial input 1 enable Serial data input 1 Serial input 1 acknowledge Serial 2 clock input Serial output 2 enable Serial data output 2
SIEN2 SI2
47 48
H5 F6
Serial input 2 enable Serial data input 2
Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state on completion of data transfer and input of the hardware reset (RESET) signal.
12
Data Sheet U14373EJ3V0DS
PD77113A, 77114
* Host interface
Pin No. Pin Name 100-pin TQFP HA1 72 80-pin BGA B8 Input Specifies the register to be accessed by HD7 through HD0. * 1: Accesses the host interface status register (HST). * 0: Accesses the host transmit data register (HDT (out)) when read (HRD = 0), and host receive data register (HDT (in)) when written (HWR = 0). Specifies the register to be accessed by HD7 through HD0. * 1: Accesses bits 15 through 8 of HST, HDT (in), and HDT (out). * 0: Accesses bits 7 through 0 of HST, HDT (in), and HDT (out). Chip select input Host read input Host write input Host read enable output Host write enable output 8-bit host data bus - I/O Function Shared by:
HA0
71
C8
Input
-
HCS HRD HWR HRE HWE HD0 - HD7
68 69 70 66 67 63 - 56
E6 D8 D7 - - F5, E8, E9, F7, G6, F9, F8, H8
Input Input Input Output Output I/O (3S)
- - - - - -
Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state when the host interface is not being accessed. * I/O ports
Pin No. Pin Name 100-pin TQFP P0 P1 P2 P3 55 54 53 52 80-pin BGA H7 G8 G7 H6 I/O I/O I/O I/O General-purpose I/O port - - - - I/O Function Shared by:
Data Sheet U14373EJ3V0DS
13
PD77113A, 77114
* Debugging interface
Pin No. Pin Name 100-pin TQFP TDO TICE TCK TDI TMS TRST 79 80 81 82 83 84 80-pin BGA C6 B6 D5 C5 A6 A8 Output Output Input Input Input Input For debugging - - - - - - I/O Function Shared by:
* Others
Pin No. Pin Name 100-pin TQFP I.C. 98 - 80-pin BGA - - - Internally connected. Leave this pin unconnected. No function pins. Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor. - - I/O Function Shared by:
NU
A2, B1, B2, C2, C3, D2, D4, E1, E4, F1, F2, H1, H2, H9, J2, J8 -
NC -
2, 3, 49, 95 -
- -
No-connect pins. Leave these pins unconnected. Pins to strengthen soldering. Connect these pins to the board as necessary.
- -
A1, A9, J1, J9
Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal operation of the PD77113A and 77114 is not guaranteed.
14
Data Sheet U14373EJ3V0DS
PD77113A, 77114
1.2 Connection of Unused Pins
1.2.1 Connection of Function Pins When mounting, connect unused pins as follows:
Pin INT1 - INT4 X/Y DA0 - DA12 D0 - D15
Note 1
I/O Input Output Output I/O Output Input Output Input Input Input Input Output Output Output Input Input Output I/O I/O Input Output Input Input Output Connect to EVDD or GND. Connect to EVDD. Leave unconnected. Leave unconnected. Connect to GND. Connect to EVDD. Leave unconnected.
Recommended Connection
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor. Leave unconnected. Leave unconnected. (internally pulled up). Leave unconnected. Connect to EVDD or GND.
MRD, MWR HOLDRQ BSTB, HOLDAK SCK1, SCK2 SI1, SI2 SIEN1, SIEN2 SOEN1, SOEN2 SORQ1 SO1, SO2 SIAK1 HA0, HA1 HCS, HRD, HWR HRE, HWE HD0 - HD7 P0 - P3 TCK TDO, TICE TMS, TDI TRST CLKOUT
Note 2
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
Connect to GND via pull-down resistor. Leave unconnected. Leave unconnected. (internally pulled up). Leave unconnected. (internally pulled down). Leave unconnected.
Notes 1. These pins may be left unconnected if the external data memory is not accessed in the program. However, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 2. These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level. However, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered.
Data Sheet U14373EJ3V0DS
15
PD77113A, 77114
1.2.2 Connection of no-function pins
Pin I.C. NU NC I/O - - - Leave unconnected. Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor. Leave unconnected. Recommended Connection
16
Data Sheet U14373EJ3V0DS
PD77113A, 77114
2. FUNCTION OUTLINE 2.1 Program Control Unit
This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode of the DSP. 2.1.1 CPU control A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as branch instructions, are executed in one system clock. 2.1.2 Interrupt control Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial interface and host interface) are serviced. Multiple interrupts are also supported. 2.1.3 Loop control task A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support multiple loops. 2.1.4 PC stack A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls. 2.1.5 PLL A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating clock to the DSP. A multiple of x1 to x16 or a division ratio of 1/1 to 1/16 can be set by a mask option. Two standby modes are available for lowering the power consumption while the DSP is not in use. * HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The normal operation mode is recovered by an interrupt or hardware reset. * STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10 A. The normal operation mode is recovered by hardware reset or WAKEUP pin Note If the WAKEUP function is activated by mask option 2.1.6 Instruction memory The capacity and type of the memory differ depending on the model of the DSP. 64 words of the instruction RAM are allocated to interrupt vectors. A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface). The PD77113A and 77114 have 3.5K-word instruction RAM and 48K-word instruction ROM.
Note
The interrupt of each interrupt source can be enabled or disabled.
.
Data Sheet U14373EJ3V0DS
17
PD77113A, 77114
2.2 Arithmetic Unit
This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 General-purpose registers (R0 through R7) These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to data memory. A general-purpose register (R0 to R7) is made up of three parts: R0L through R7L (bits 15 through 0), R0H through R7H (bits 31 through 16), and R0E through R7E (bits 39 through 32). Depending on the type of operation, RnL, RnH, and RnE are used as one register or in different combinations. 2.2.2 Multiply accumulator (MAC) The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and outputs a 40-bit value. The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right . 2.2.3 Arithmetic logic unit (ALU) This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value. 2.2.4 Barrel shifter (BSFT: Barrel ShiFTer) The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value. The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or logically shifted to the right, in which case 0 is inserted from the MSB.
18
Data Sheet U14373EJ3V0DS
PD77113A, 77114
2.3 Data Memory Unit
The data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 Data memory The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space. The PD77113A and 77114 have 16K words x 2 banks data RAM and 32K words x 2 banks data ROM. In addition, the PD77114 has an external data memory interface so that the external memory can be expanded to 8K words x 2 banks. 2.3.2 Data addressing unit An independent data addressing unit is provided for each of the X data memory and Y data memory spaces. Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or DMY), and an address ALU.
2.4 Peripheral Units
A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as memory-mapped I/Os. 2.4.1 Serial interface (SIO) Two serial interfaces are provided. These serial interfaces have the following features: * Serial clock : Supplied from external source to each interface. The same clock is used for input and output on the interface. * Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output * Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the internal units, polling, wait, or interrupt are used. 2.4.2 Host interface (HIO) This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of polling, wait, or interrupts. 2.4.3 General-purpose I/O port (PIO) This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units. 2.4.4 Wait cycle register The number of wait cycles to be inserted when the external data memory area is accessed can be specified in advance by using a register (DWTR)
Note
. The number of wait cycles that can be set is 1, 3, or 7.
Note This function is not available on the PD77113A because this DSP does not have an external data area.
Data Sheet U14373EJ3V0DS
19
PD77113A, 77114
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and supplies the generated clock to the internal units of the DSP. For details of how to set the PLL multiple, refer to 4.2 Initializing PLL, and 8.1 Clock Control Options.
Stop mode Halt mode
CLKIN
PLL control circuit xm
Output divider /n
Halt divider /l
Internal system clock
CLKOUT
4. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
4.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction at address 0x200 of instruction memory (reset entry). In addition, a self-check is performed by the internal data RAM at the same time as the boot processing. This check takes about 20 ms (at 50 MHz operation, the length of this period is in inverse proportion to the operating frequency.) On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.
20
Data Sheet U14373EJ3V0DS
PD77113A, 77114
4.2 Initializing PLL
Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level). Initialization takes 1024 clocks and it takes the PLL 100 s to be locked. After that, the DSP operates with the set value of the PLL specified by a mask option when the RESET pin is deasserted inactive (high level). After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the PLL, the internal memory contents and register status of the DSP are not retained. If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the PLL is not initialized).
CLKIN 1 RESET 1024 2048 Approx. 100 s PLL lock time PLL initialization (internal status) PLL initialization mode
Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock period.
5. FUNCTIONS OF BOOT-UP ROM
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction RAM by using the internal boot-up ROM. The PD77113A and 77114 have a function to verify the contents of the internal instruction RAM and a function to modify the instruction ROM in the boot-up ROM.
5.1 Boot at Reset
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and, depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN). If host boot or self boot is specified, a self-check of the internal data RAM is performed at the same time as boot processing.
P1 0 0 1 1 P0 0 1 1 0 Boot Mode Does not execute boot but branches to address 0x200
Note
.
Executes host boot and then branches to address 0x200. Executes self boot and then branches to address 0x200. Setting prohibited
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has been executed once.
Data Sheet U14373EJ3V0DS
21
PD77113A, 77114
5.1.1 Self boot The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model, this function is implemented by storing the instructions to be booted in the data ROM. In addition, the instructions to be booted can be also stored in an external data area in the form of flash ROM, and self boot can be executed from this external data area. 5.1.2 Host boot In this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the instruction RAM.
5.2 Reboot
By calling the next reboot entry from the program, the contents of the instruction RAM can be rewritten.
Reboot Mode Self boot X memory Word reboot Byte reboot Y memory Word reboot Byte reboot Host boot Host reboot Entry Address 0x2 0x4 0x1 0x3 0x5
5.2.1 Self reboot The instruction codes stored in the data memory are transferred to the instruction RAM. Set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot. * R7L : Number of instruction steps for rebooting * DP3: First address of X memory in which instruction codes are stored (in the case of reboot from X memory), or first address of the instruction memory to be loaded (in the case of reboot from Y memory) * DP7: First address of instruction memory to be loaded (in the case of reboot from X memory), or first address of X memory in which instruction codes are stored (in the case of reboot from Y memory) 5.2.2 Host reboot An instruction code is obtained via the host interface and transferred to the instruction RAM. The entry address of is 0x5. Host reboot is executed by calling this address after setting the following parameter: * R7L : Number of instruction steps for rebooting * DP3: First address of instruction memory to be loaded
22
Data Sheet U14373EJ3V0DS
PD77113A, 77114
5.3 Signature Operation
The PD77113A and 77114 have a signature operation function so that the contents of the internal instruction RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the operation result with the previous result. If the results are identical, there is no problem. The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The operation result is stored in register R7. * R7L: Number of instruction steps for operation * DP3: First address of instruction memory for operation
5.4 Instruction ROM Modification
The PD77113A and 77114 have a function to modify the contents of the internal instruction mask ROM. Instructions at up to four addresses can be modified. The entry address is 0x10D. By calling this address with the following parameters, modification is performed. R7L : Address of instruction ROM to be modified
R6H, R6L : Instruction code (32 bits)
Data Sheet U14373EJ3V0DS
23
PD77113A, 77114
6. STANDBY MODES
Two standby modes are available. By executing the corresponding instruction, each mode is set and the power consumption can be reduced.
6.1 HALT Mode
To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are stopped to reduce the current consumption. To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release the HALT mode when the HALT mode is released using an interrupt. In the HALT Mode, the clock circuit of the PD77111 family supplies the following clock as the internal system clock. The clock output from the CLKOUT pin is also as follows. The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal operation (i.e., the duty factor is not 50%).
* PD77113A, 77114: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)
6.2 STOP Mode
To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and PLL, are stopped and the power consumption is minimized with only leakage current flowing. To release the STOP mode, use hardware reset or WAKEUP pin. When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are retained, but it takes several 100 s to release the mode. The WAKEUP pin is multiplexed with the INT4 pin. Usually, this pin functions as an interrupt pin, but functions as the WAKEUP pin when it is asserted active in the STOP mode. Whether the WAKEUP pin is used to release the STOP mode is selected by mask option. For details, refer to 8.2 WAKEUP Function.
24
Data Sheet U14373EJ3V0DS
PD77113A, 77114
7. MEMORY MAP
A Harvard architecture, in which the instruction memory space and data memory space are separated is employed.
7.1 Instruction Memory
7.1.1 Instruction memory map The instruction memory space consists of 64K words x 32 bits, and the capacity and type of the memory differ depending on the product.
PD77113A, 77114
0 x FFFF
Internal instruction ROM (48K words)
0x4000 0 x 3FFF System 0x1000 0 x 0 F F F Internal instruction RAM (3.5K words) 0x0240 0x023F Vector area (64 words) 0x0200 0 x 0 1FF System 0x0100 0 x 0 0FF Boot-up ROM (256 words) 0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed.
Data Sheet U14373EJ3V0DS
25
PD77113A, 77114
7.1.2 Interrupt vector table Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts. instruction addresses are assigned to each interrupt source.
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C INT1 INT2 INT3 INT4 SI1 input SO1 output SI2 input SO2 output HI input HO output Reserved Reset Reserved Interrupt Source
Four
Cautions
1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector. 2. It is recommended that unused interrupt source vectors be used to branch an error processing routine. 3. Because a vector area also exists in the internal RAM area of the mask ROM model, this area must be booted up. not used. In addition, because the entry address after reset is 0x200, address 0x200 must be booted up even when the internal instruction RAM and interrupts are
26
Data Sheet U14373EJ3V0DS
PD77113A, 77114
7.2 Data Memory
7.2.1 Data memory map The data memory space consists of an X memory space and a Y memory space of 64K words x 16 bits each, and the memory capacity and memory type differ depending on the product.
PD77113A
0 x FFFF 0 xE0 0 0 0 x DF F F Data RAM (8K words) System 0 xC0 0 0 0 x BFFF Data RAM (8K words) External data memory (8K words)
PD77114
Data ROM (32K words)
Data ROM (32K words)
0x4000 0 x 3FFF 0x3840 0x383F 0x3800 0 x 3 7FF 0x3000 0 x 2FFF 0x2000 0 x 1FFF 0x1000 0 x 0FFF 0x0000
System Peripheral (64 words) System Data RAM (4K words) System Data RAM (4K words)
System Peripheral (64 words) System Data RAM (4K words) System Data RAM (4K words)
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed.
Data Sheet U14373EJ3V0DS
27
PD77113A, 77114
7.2.2 Internal peripherals The internal peripherals are mapped to the internal data memory space.
X/Y Memory Address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x3809 - 0x383F Register Name SDT1 SST1 SDT2 SST2 PDT PCD HDT HST DWTR Reserved area First serial data register First serial status register Second serial data register Second serial status register Port data register Port command register Host data register Host status register Data memory wait cycle register Caution Do not access this area. WTR - HIO PIO Function Peripheral Name SIO
Cautions
1. The register names listed in this table are not reserved words of the assembler or the C language. Therefore, when using these names in assembler or C, the user must define them. 2. The same register is accessed, as long as the address is the same, regardless of whether the X memory space or Y memory space is accessed. 3. Even different registers cannot be accessed at the same time from both the X and Y memory spaces.
8. MASK OPTION
The PD77113A and 77114 have mask options that must be specified when an order for a ROM is placed. This section explains these mask options. The mask options are specified in the Workbench (WB77016) development tool. To order a mask ROM, output a mask ROM ordering file format (.msk file) using WB77016.
8.1 Clock Control Options
The following four clock related options must be specified. * PLL multiple * Output division ratio * HALT division ratio * Validity of CLKOUT pin
28
Data Sheet U14373EJ3V0DS
PD77113A, 77114
When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each operation mode and operating clock is as follows:
Operation Mode Normal operation mode HALT mode STOP mode Clock Supplied Inside DSP m/n times external input clock m/n/l times external input clock Stopped
The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL multiple so that the multiplied frequency falls within the specified PLL lock frequency range. The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the specified operating frequency range of the DSP. The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1 to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so that necessary division can be performed. Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is "output" or "not output" from the CLKOUT pin can be specified. Specify the mask option as necessary. If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%).
8.2 WAKEUP Function
The WAKEUP pin can be used to release the STOP mode as well as a hardware reset. If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP mode is set can be retained and program execution can be resumed starting from the instruction after the STOP instruction. Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option. When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt vector).
Data Sheet U14373EJ3V0DS
29
PD77113A, 77114
9. INSTRUCTIONS 9.1 Outline of Instructions
An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are executed with one system clock. The maximum instruction cycle of the PD77113A and 77114 is 13.3 ns. The following nine types of instructions are available: (1) Trinomial operation instructions These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be specified. (2) Binomial operation instructions These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose registers can be specified. An immediate value can be specified for some of these instructions, instead of a general-purpose register, for one input. (3) Uninominal operation instructions These instructions specify an operation by the ALU. As the operands, one general-purpose register can be specified. (4) Load/store instructions These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose register can be specified as the transfer source or destination. (5) Register-to-register transfer instructions These instructions transfer data from one general-purpose register to another. (6) Immediate value setting instructions These instructions write an immediate value to a general-purpose register and the registers of the address operation unit. (7) Branch instructions These instruction specify branching of program execution. (8) Hardware loop instructions These instruction specify repetitive execution of an instruction. (9) Control instructions These instructions are used to control the program.
30
Data Sheet U14373EJ3V0DS
PD77113A, 77114
9.2 Instruction Set and Operation
An operation is written in the operation field for each instruction in accordance with the operation representation format of that instruction. If two or more parameters can be written, select one of them. (a) Representation formats and selectable registers The following table shows the representation formats and selectable registers.
Representation Format r0, r0, r0 rI, rI rh, rh re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm *xxx R0 - R7 R0L - R7L R0H - R7H R0E - R7E R0EH - R7EH DP0 - DP7 DN0 - DN7 DMX, DMY DP0 - DP3 DP4 - DP7 DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 0 - 3) DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 4 - 7) DPn##imm (n = 0 - 7) Contents of memory with address xxx If the contents of the DP0 register are 1000, *DP0 indicates the contents of address 1000 of the memory. Selectable Register
Data Sheet U14373EJ3V0DS
31
PD77113A, 77114
(b) Modifying data pointer The data pointer is modified after the memory has been accessed. The result of modification becomes valid starting from the instruction that immediately follows. The data pointer cannot be modified.
Example DPn DPn++ DPn-- DPn## Operation Nothing is done (value of DPn is not changed.) DPn DPn + 1 DPn DPn - 1 DPn DPn + DNn (Adds value of corresponding DN0 to DN7 to DP0 to DP7.) Example: DP0 DP0 + DN0 (n = 0 - 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH (n = 4 - 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH !DPn## Reverses bits of DPn and then accesses memory. After memory access, DPn DPn + DNn DPn DPn + imm
DPn%%
DPn##imm
(c) Instructions that can be simultaneously written Instructions that can be simultaneously written are indicated by . (d) Status of overflow flag (OV) The status of the overflow flag is indicated by the following symbol: z: Not affected : Set to 1 when overflow occurs Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but retains the status before the operation.
32
Data Sheet U14373EJ3V0DS
PD77113A, 77114
Instruction Set
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control
Flag
Loop
OV
Trinomial operation
Multiply add Multiply sub Sign unsign multiply add
ro = ro + rh * rh ro = ro - rh * rh ro = ro + rh * rl (rl is in positive integer format.)
ro ro + rh * rh ro ro - rh * rh ro ro + rh * rl

Unsign unsign multiply add
1-bit shift multiply add 16-bit shift multiply add Binomial operation Multiply Add Immediate add
ro = ro + rl * rl ro ro + rl * rl (rl and rl' are in positive integer format.) ro ro 2 + rh * rh ro = (ro>>1) + rh * rh ro = (ro>>16) + rh * rh
ro ro 216 + rh * rh
z z
ro = rh * rh ro = ro + ro ro = ro + imm ro = ro - ro ro = ro - imm
ro rh * rh ro ro + ro ro ro + imm (where imm 1) ro ro - ro ro ro - imm (where imm 1) ro ro >> rl ro ro >> imm
Sub Immediate sub
Arithmetic right shift Immediate arithmetic right shift Logical right shift Immediate logical right shift
ro = ro SRA rl
z z
ro = ro SRA imm
ro = ro SRL rl
ro ro >> rl ro ro >> imm
z z
ro = ro SRL imm
Logical left shift ro = ro SLL rl Immediate logical left shift AND Immediate AND OR Immediate OR Exclusive OR Immediate exclusive OR ro = ro SLL imm
ro ro << rl ro ro << imm ro ro & ro ro ro & imm ro ro ro ro ro imm ro ro ro ro ro imm
z z
ro = ro & ro ro = ro & imm ro = ro ro ro = ro imm ro = ro ro ro = ro imm
z z
z z
z z
Data Sheet U14373EJ3V0DS
33
PD77113A, 77114
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control
Flag
Loop
OV
Binomial operation
Less than
ro = LT (ro, ro)
if (ro < ro) {ro 0x0000000001} else {ro 0x0000000000} ro 0x0000000000 ro ro + 1 ro ro - 1 if (ro < 0) {ro -ro} else {ro ro} ro ~ro ro -ro
z
Uninominal operation
Clear Increment Decrement Absolute value
CLR (ro) ro = ro + 1 ro = ro - 1 ro = ABS (ro)

z
1's complement 2's complement Clip
ro = ~ro ro = -ro

z
ro = CLIP (ro)
if ( ro > 0x007FFFFFFF) {ro 0x007FFFFFFF} elseif {ro < 0xFF80000000} {ro 0xFF80000000} else {ro ro}
z
Round
ro = ROUND (ro)
if (ro > 0x007FFF0000) {ro 0x007FFF0000} elseif {ro < 0xFF80000000} {ro 0xFF80000000} else {ro (ro + 0x8000) & 0xFFFFFF0000} 1 ro log2 ( ro) ro ro ro ro + ro ro ro - ro if (sign (ro) == sign (ro)) {ro (ro - ro) << 1} else {ro (ro + ro)<<1} if (sign (ro)==0) {ro ro + 1}
z
Exponent Substitution Accumulated addition Accumulated subtraction Division
ro = EXP (ro) ro = ro ro + = ro ro - = ro

z z
ro / = ro
34
Data Sheet U14373EJ3V0DS
PD77113A, 77114
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control
Flag
Loop
OV
Load/ store
Parallel Notes 1, 2 load/store
ro = *dpx_mod ro = *dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = rh ro = *dpy_mod *dpx_mod = rh *dpy_mod = rh
ro *dpx, ro *dpy ro *dpx, *dpy rh *dpx rh, ro *dpy *dpx rh, *dpy rh dest *dpx, dest *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source dest *addr *addr source dest *dp *dp source dest rl rl source rl imm dp imm dn imm dm imm
z
Partial load/ Notes 1, 2, 3 store
dest = *dpx_mod dest = *dpy_mod dest = *dpx_mod *dpy_mod = source *dpx_mod = source dest = *dpy_mod *dpx_mod = source *dpy_mod = source
z
Direct addressing Note 4 load/store Immediate value index Note 5 load/store Register- Register-toto-register register Note 6 transfer transfer Immediate value setting Immediate value setting
dest = *addr *addr = source dest = *dp_imm *dp_imm = source dest = rl rl = source rl = imm (where imm = 0 to 0xFFFF) dp = imm (where imm = 0 to 0xFFFF) dn = imm (where imm = 0 to 0xFFFF) dm = imm (where imm = 1 to 0xFFFF)
z
z
z
z
Notes 1. Of the two mnemonics, either one of them or both can be written. 2. After transfer, modification specified by mod is performed. 3. Select any of dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}. 0: X-0xFFF : X (X memory) . 4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = 0: Y-0xFFFF : Y (Y memory) 5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 6. Select any register other than general-purpose registers as dest and source.
Data Sheet U14373EJ3V0DS
35
PD77113A, 77114
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control
Flag
Loop
OV
Branch Jump Register indirect jump Subroutine call
JMP imm JMP dp
PC imm PC dp SP SP + 1 STK PC + 1 PC imm SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Recovery of interrupt enable flag Start During repeat End RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1

z z z
CALL imm
Register indirect subroutine call Return
CALL dp
z
RET

z z
Interrupt return
RETI
Hardware loop
Repeat
REP count
z
Loop
LOOP count (instruction of two or more lines)
Start During repeat End
z
Loop hop
LPOP
LC LSR3 LE LSR2 LS LSR1 LSP LSP - 1 PC PC + 1 CPU stops. CPU, PLL, and OSC stop. Condition test Discard interrupt request
z
Control No operation Halt Stop
NOP HALT STOP
z z z z z
Condition
IF (ro cond)
Forget interrupt FINT
36
Data Sheet U14373EJ3V0DS
PD77113A, 77114
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C)
Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating temperature VI VO Tstg TA Condition For DSP core For I/O pins VI < EVDD + 0.5 V Rating - 0.5 to +3.6 -0.5 to +4.6 -0.5 to +4.1 -0.5 to +4.1 -65 to +150 -40 to +85 Unit V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used unber conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions
Parameter Operating voltage Symbol IVDD EVDD Condition For DSP core For I/O pins IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 0 MIN. 1.8 2.7 TYP. MAX. 2.7 3.3 3.6 EVDD V Unit V V
Input voltage
VI
Capacitance (TA = +25C, IVDD = 0 V, EVDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Condition f = 1 MHz, Pins other than those tested: 0 V MIN. TYP. 10 10 10 MAX. Unit pF pF pF
Data Sheet U14373EJ3V0DS
37
PD77113A, 77114
DC Characteristics (Unless otherwise specified, TA = -40 to +85C, with IVDD and EVDD within recommended operating condition range)
Parameter High-level input voltage Symbol VIHN VIHS Condition Pins other than below CLKIN, RESET, INT1 - INT4, SCK1, SIEN1, SOEN1, SCK2, SIEN2, SOEN2 CLKIN MIN. 0.7 EVDD 0.8 EVDD TYP. MAX. EVDD EVDD Unit V V
VIHC
0.5 EVDD +0.25 0 0
EVDD
V
Low-level input voltage
VIL VIC
Pins other than below CLKIN IOH = -2.0 mA IOH = -100 A
0.2 EVDD 0.5 EVDD -0.25
V V
High-level output voltage
VOH
0.7 EVDD 0.8 EVDD 0.2 EVDD 0 -10 -250 0 TBD 10
V V V
Low-level output voltage High-level input leakage current Low-level input leakage current Pull-up pin current Pull-down pin current Internal supply current [VIHN = VIHS = EVDD, VIL = 0 V, no load]
VOL ILH
IOL = 2.0 mA Other than TDI, TMS, and TRST VI = EVDD Other than TDI, TMS, and TRST VI = 0 V TDI, TMS, 0 V VI EVDD TRST, 0 V VI EVDD During operating, 30 ns, IVDD = 2.7 V In halt mode, tcC = 30 ns, divided by eight, IVDD = 2.7 V In stop mode, 0C < TA < 60C
A A A A
mA
ILL
0
IPUI IPDI IDD
Note
0 250 75
IDDH
TBD
10
mA
IDDS
100
A
Note The TYP. values are when an ordinary program is executed. The MAX. values are when a special program that brings about frequent switching inside the device is executed.
38
Data Sheet U14373EJ3V0DS
PD77113A, 77114
Common Test Criteria of Switching Characteristics
CLKIN, RESET, INT1 - INT4, SCK1, SIEN1, SOEN1, SCK2, SIEN2, SOEN2 0.8 EVDD 0.5 EVDD 0.2 EVDD 0.8 EVDD 0.5 EVDD 0.2 EVDD
Test points
Input (other than above)
0.7 EVDD 0.5 EVDD 0.2 EVDD
Test points
0.7 EVDD 0.5 EVDD 0.2 EVDD
Output
0.5 EVDD
Test points
0.5 EVDD
Data Sheet U14373EJ3V0DS
39
PD77113A, 77114
PD77113A, 77114
AC Characteristics (TA = -40 to +85C, with IVDD and EVDD within recommended operating condition range) Clock Timing requirements
Parameter CLKIN cycle time
Note 1
Symbol tcCX
Condition
MIN. 25
TYP.
MAX.
Unit ns
PLL lock Note 2 range
IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V
25 x m 10 x m
50 x m 50 x m
ns
ns
CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time Note 3 requirements
twCXH twCXL trfCX tcC (R) IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V
12.5 12.5 5 25 13.3
ns ns ns ns ns
Notes 1. m: Multiple, n: Division ratio 2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range. 3. Input tcCX so that the value of (tcCX / m x n) satisfies this condition. Switching characteristics
Parameter Internal clock cycle
Note
Symbol tcC
Condition During normal operation In HALT mode
MIN.
TYP. tcCX x n / m tcCX x n / m x l tcC
MAX.
Unit ns ns ns ns ns
CLKOUT cycle time CLKOUT width
tcCO twCO During normal operation n = 1, or even number n = odd number (other than 1) tcC / 2 - 3 tcC / n / 2 - 3 tcC / n / 2 - 3
In HALT mode CLKOUT rise/fall time CLKOUT delay time trfCO tdCO IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V
ns 5 20 15 ns ns ns
Note m: Multiple, n: Division ratio, l: HALT division ratio
40
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Clock I/O timing
tcCX twCXH twCXL trfCX trfCX
CLKIN
tcC, tcC(R)
Internal clock
tcCO tdCO twCO twCO trfCO trfCO
CLKOUT
Data Sheet U14373EJ3V0DS
41
PD77113A, 77114
PD77113A, 77114
Reset, Interrupt Timing requirements
Parameter RESET low-level width Symbol tw (RL) Condition On power application in STOP mode During normal operation, in HALT mode RESET recovery time trec (R) On power application
Note 4 Note 1
MIN. , 100 + 2048tcCX 4tcC
Note 2
TYP.
MAX.
Unit
s
Note 3 ns
4tcCX 4tcC
Note 2
ns ns
WAKEUP low-level width INT1 - INT4 low-level width INT1 - INT4 recovery time
tw (WAKEUPL) tw (INTL) trec (INT)
100 3tcC
Note 2
s
ns ns
3tcC
Notes 1. The value on power application is the time from when the supply voltages have reached IVDD = 1.8 V and EVDD = 2.7 V. A stable clock input is also required. 2. Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode. 3. If the low-level width of RESET is greater than 1024tcC, the PLL initialization mode is triggered. If there is no need to use the PLL initialization mode, set the width to less than 1024tcC. 4. When the power is turned on, a recovery period of 4tcCX is necessary before inputting RESET. Reset timing
tw(RL) RESET trec(R)
WAKEUP timing
tw (WAKEUPL) WAKEUP
Interrupt timing
trec(INT) tw(INTL) INT1 - INT4
42
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
External Data Memory Access (PD77114 only) Timing requirements
Parameter Read data setup time Read data hold time Symbol tsuDDRD thDDRD Condition MIN. 18 0 TYP. MAX. Unit ns ns
Switching characteristics
Parameter Address cycle time Address output hold time MRD output delay time Write data output valid time Write data output hold time MWR output delay time MWR output hold time MWR low-level width MWR high-level width Symbol trcDA thDA tdDR tvDDWD thDDWD tdDW thDA twDWL twDWH 0 0 0 tcC x tcDW - 3 0.5 tcC - 3 0.5 tcC 0 5 5 Condition MIN. TYP. tcC + (tcC x tcDW)
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns
Note tcDW: Number of data wait cycles
Data Sheet U14373EJ3V0DS
43
PD77113A, 77114
PD77113A, 77114
External data memory access timing (read)
DA0 - DA12 X/Y trcDA
tdDR MRD
tdDR
tsuDDRD D0 - D15
thDDRD
External data memory access timing (write)
DA0 - DA12 X/Y trcDA tdDW twDWL twDWH tdDW thDA
MWR tvDDWD D0 - D15 Hi-Z tvDDWD thDDWD Hi-Z
44
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Bus Arbitration (PD77114 only) Timing requirements
Parameter HOLDRQ setup time HOLDRQ hold time Symbol tsuHRQ thHRQ Condition MIN. 0 0 TYP. MAX. Unit ns ns
Switching characteristics
Parameter BSTB hold time BSTB output delay time HOLDAK output delay time Data hold time during bus arbitration Data valid time during bus arbitration Symbol thBS tdBS tdHAK th (BS-D) Condition MIN. 0 20 18 25 TYP. MAX. Unit ns ns ns ns
tv (BS-D)
25
ns
Data Sheet U14373EJ3V0DS
45
PD77113A, 77114
PD77113A, 77114
Bus arbitration timing (when bus is idle)
CLKIN (Bus busy) thBS BSTB tsuHRQ HOLDRQ tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA12, MRD, MWR Hi-Z tv (BS-D) tdHAK thHRQ tsuHRQ thHRQ Bus idle tdBS Bus release Bus idle (Bus busy)
Bus arbitration timing (when bus is busy)
CLKIN
(Bus busy)
Bus busy
Bus idle
Bus release
Bus idle
(Bus busy)
thBS BSTB tsuHRQ HOLDRQ
tdBS
tsuHRQ thHRQ
thHRQ
tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA12, MRD, MWR Hi-Z
tdHAK
tv (BS-D)
46
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Serial Interface Timing requirements
Parameter SCK cycle time SCK high-/low-level width SCK rise/fall time SOEN setup time Symbol tcSC twSC trfSC tsuSOE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SOEN hold time thSOE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIEN setup time tsuSIE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIEN hold time thSIE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SI setup time tsuSI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SI hold time thSI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 10 5 15 10 10 5 15 10 10 5 15 10 Condition MIN. 60 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter SORQ output delay time Symbol tdSOR Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SORQ hold time SO output delay time thSOR tdSO IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SO hold time SIAK output delay time thSO tdSIA IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIAK hold time thSIA 0 0 30 25 0 30 25 MIN. TYP. MAX. 30 25 Unit ns ns ns ns ns ns ns ns ns
Data Sheet U14373EJ3V0DS
47
PD77113A, 77114
PD77113A, 77114
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: * Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). * Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source. * Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. * Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-toone basis. Do not supply clock to several devices from one clock source. * Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear.
x Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock.
x The serial clock must not rise or fall step-wise.
48
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Serial output timing 1
tcSC twSC SCK1, SCK2 twSC trfSC trfSC
tdSOR
thSOR
SORQ1 tsuSOE tsuSOE thSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Hi-Z 1st tdSO Last thSO
Serial output timing 2 (during successive output)
tcSC twSC SCK1, SCK2 twSC trfSC trfSC
tdSOR
thSOR
SORQ1 tsuSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Last 1st Last thSO
Data Sheet U14373EJ3V0DS
49
PD77113A, 77114
PD77113A, 77114
Serial input timing 1
tcSC twSC SCK1, SCK2 twSC trfSC trfSC
tdSIA
thSIA
SIAK1 tsuSIE tsuSIE SIEN1, SIEN2 thSIE thSIE
tsuSI SI1, SI2 1st
thSI 2nd 3rd
Serial input timing 2 (during successive input)
tcSC twSC SCK1, SCK2 twSC trfSC trfSC
tdSIA
thSIA
SIAK1 tsuSIE thSIE SIEN1, SIEN2 tsuSI SI1, SI2 thSI
Last-1
Last
1st
2nd
3rd
50
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Host Interface Timing requirements
Parameter HRD delay time Symbol tdHR Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD width HCS, HA0, HA1, read hold time HCS, HA0, HA1 write hold time HRD, HWR recovery time HWR delay time twHR thHCAR MIN. 15 10 60 0 TYP. MAX. Unit ns ns ns ns
thHCAW trecHS tdHW IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V
0 60 15 10 60 0 IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 15 10
ns ns ns ns ns ns ns ns
HWR width HWR hold time HWR setup time
twHW thHDW tsuHDW
Switching characteristics
Parameter HRE, HWE output delay time Symbol tdHE Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRE, HWE hold time thHE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD valid time tvHDR IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD hold time thHDR 0 MIN. TYP. MAX. 30 25 30 25 30 25 Unit ns ns ns ns ns ns ns
Data Sheet U14373EJ3V0DS
51
PD77113A, 77114
PD77113A, 77114
Host read interface timing
CLKIN
HCS, HA0, HA1 thHCAR tdHR HRD thHDR Hi-Z tdHE tvHDR Hi-Z twHR trecHS
HD0 - HD7
thHE
HRE
Host write interface timing
CLKIN
HCS, HA0, HA1 thHCAW tdHW HWR thHDW tsuHDW HD0 - HD7 tdHE twHW trecHS
thHE
HWE
52
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
General-purpose I/O Port Timing requirements
Parameter Port input setup time Port input hold time Symbol tsuPI thPI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Condition MIN. 0 15 10 TYP. MAX. Unit ns ns ns
Switching characteristics
Parameter Port output delay time Symbol tdPO Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 30 25 Unit ns ns
General-purpose I/O port timing
CLKIN
tdPO P0 - P3 (Output) tsuPI thPI P0 - P3 (Input)
Data Sheet U14373EJ3V0DS
53
PD77113A, 77114
PD77113A, 77114
Debugging Interface (JTAG) Timing requirements
Parameter TCK cycle time TCK high-/low-level width TCK rise/fall time TMS, TDI setup time Symbol tcTCK twTCK trfTCK tsuDI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V TMS, TDI hold time thDI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Input pin setup time tsuJIN IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Input pin hold time thJIN IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V TRST setup time tsuTRST 25 20 25 20 25 20 25 20 100 Condition MIN. 120 50 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter TDO output delay time Symbol tdDO Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Output pin output delay time tdJOUT IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 25 20 25 20 Unit ns ns ns ns
54
Data Sheet U14373EJ3V0DS
PD77113A, 77114
PD77113A, 77114
Debugging interface timing
tcTCK twTCK twTCK trfTCK trfTCK
TCK
tsuTRST
TRST tsuDI thDI
TMS, TDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
Data Sheet U14373EJ3V0DS
55
PD77113A, 77114
11. PACKAGE DRAWINGS
80-PIN PLASTIC FBGA (9x9)
A B
W
SB
B
A C D
9 8 7 6 5 4 3 2 1
JHGFEDCBA Q Index mark P W SA J I R Y1 S H
ITEM A B C D MILLIMETERS 9.000.10 8.40 8.40 9.000.10 1.30 0.8 (T.P.) 0.350.1 0.36 0.96 1.310.15 0.10
S
E F G
K
S
F L
E
G
H I J K L M P Q R W Y1
M M
SAB
0.50+0.05 -0.10
0.08 C1.0 R0.3 25 0.20 0.20 S80F1-80-CN1-1
56
Data Sheet U14373EJ3V0DS
PD77113A, 77114
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D Q R
100 1
26 25
F G H P I
M
J
K
N
S
L M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.00.1 0.10.05 +7 3 -3 1.27 MAX. S100GC-50-9EU-2
Data Sheet U14373EJ3V0DS
57
PD77113A, 77114
12. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Surface mount type
PD77113AF1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 x 9)
Soldering Method Infrared reflow Soldering Conditions Recommended Condition Symbol IR30-103-2
Package peak temperature: 230C, Time: 30 sec. Max. (at 210C or higher). Count: two times or less Exposure limit: 3 days
Note
(after that prebake at 125C for 10 hours)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
PD77114GC-xxx-9EU: 100-pin plastic TQFP (fine-pitch) (14 x 14)
Soldering Method Infrared reflow Soldering Conditions Recommended Condition Symbol IR35-103-2
Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher). Count: two times or less Exposure limit: 3 days
Note
(after that prebake at 125C for 10 hours) VP15-103-2
VPS
Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher). Count: two times or less Exposure limit: 3 days
Note
(after that prebake at 125C for 10 hours) -
Partial heating
Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row)
Note After opening the dry pack, store is at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating for pins).
58
Data Sheet U14373EJ3V0DS
PD77113A, 77114
[MEMO]
Data Sheet U14373EJ3V0DS
59
PD77113A, 77114
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
60
Data Sheet U14373EJ3V0DS
PD77113A, 77114
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U14373EJ3V0DS
61
PD77113A, 77114
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of January, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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